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| (R) HS-83C55RH Radiation Hardened ED 16K Bit CMOS ROM ND September 1997 ME GNS at OM ESI ter c r CD n ts H o Ce / RE Features Pinout OT NEW 5647R pport l.com N R 6 u si FO HS- cal S inter HS-83C55RH 40 LEAD BRAZE SEAL DIP * Radiation Hardened EPI-CMOS . E hni ww SE ec COMPLIANT OUTLINE D5, CONFIGURATION 3 - Total Dose 1 x 105 RAD(Si) rw T ur SIL o TOP VIEW - Transient Upset > 1 x 108 RAD(Si)/s (Ports and DDR) to 12 tac NTER - Latch-Up Free > 1 x 10 RAD(Si)/sn co 88-I CE1 1 40 VDD * 2048 Words x 8 Bits ROM 1-8 * Electrically Equivalent to Sandia SA3002 * Pin Compatible with Intel 8355 * Bus Compatible with HS-80C85RH * Single 5 Volt Power Supply * Low Standby Current 100A Max * Low Operating Current 2mA/MHz * Completely Static Design * Internal Address Latches * Two General Purpose 8-Bit I/O Ports * Multiplexed Address and Data Bus * Self Aligned Junction Isolated (SAJI) Process * Military Temperature Range -55oC to +125oC CE2 2 3 4 5 6 7 8 9 39 PB7 38 PB6 37 PB5 36 PB4 35 PB3 34 PB2 33 PB1 32 PB0 31 PA7 30 PA6 29 PA5 28 PA4 27 PA3 26 PA2 25 PA1 24 PA0 23 A10 22 A9 21 A8 CLK RESET NC READY IO/M IOR RD IOW 10 ALE 11 AD0 12 AD1 13 AD2 14 AD3 15 AD4 16 AD5 17 AD6 18 AD7 19 GND 20 Description The HS-83C55RH is a radiation hardened ROM and I/O chip fabricated using the Intersil radiation hardened Self-Aligned Junction Isolated (SAJI) silicon gate technology. Latch-up free operation is achieved by the use of epitaxial starting material to eliminate the parasitic SCR effect seen in conventional bulk CMOS devices. The HS-83C55RH is intended for use with the HS-80C85RH radiation hardened microprocessor system. The ROM portion is designed as 16,384 mask programmable cells organized in a 2048 word x 8-bit format. A maximum post irradiation access time of 340ns allows the HS-83C55RH to be used with the HS-80C85RH CPU without any wait states. This ROM is designed for operation utilizing a single 5 volt power supply. Block Diagram CLK READY AD0-7 A8-10 CE2 CE1 IO/M ALE RD IOW RESET IOR VDD CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved 11-1 PORT A 2K X 8 ROM A (8) PA0-7 PORT B B (8) PB0-7 File Number 3045.2 HS-83C55RH Pin Description SYMBOL ALE PIN NUMBER 11 TYPE I DESCRIPTION Address Latch Enable: When high, AD0-7, IO/M, A8-0, CE2, and CE1, enter the address latches. The signals (AD, lO/M, A8-10, CE2, CE1) are latched in at the trailing edge of ALE.* Address/Data Bus (Bidirectional): The lower 8-bits of the ROM or I/O address are applied to the bus lines when ALE is high. During an I/O cycle, Port A or B is selected based on the latched value of AD0. If RD or IOR is low when the latched chip enables are active, the output buffers present data on the bus. Address Bus: High order bits of the ROM address. They do not affect I/O operations. Chip Enable Inputs: CE1 is active low and CE2 is active high.The HS-83C55RH can be accessed only when BOTH Chip Enables are active at the time the ALE signal latches them In. If either Chip Enable input is not active, the AD0-7 and READY outputs will be in a high impedance state. I/O Memory: If the latched IO/M is high when RD Is low, the output data comes from an I/O port. If it is low, the output data comes from the ROM. Read: If the latched Chip Enables are active when RD goes low, the AD0-7 output buffers are enabled and output either the selected ROM location or I/O port. When both RD and IOR are high, the AD0-7 output buffers are 3-stated. I/O Write: If the latched Chip Enables are active, a low on IOW causes the output port pointed to by the latched value of AD0 to be written with the data on AD0-7. The state of IO/M is ignored. Clock: Used to force the READY into its high impedance state after it has been forced low by CE1, low, CE2 high and ALE high. READY: A 3-state output controlled by CE1, CE2, ALE and CLK. READY is forced low when the Chip Enables are active during the time ALE is high, and remains low until the rising edge of the next CLK. Port A: General purpose I/O pins. Their input/output direction is determined by the contents of the Data Direction Register (DDR). Port A is selected for write operations when the Chip Enables are active and IOW is low and a 0 was previously latched from AD0, AD1. Read operation is selected by either IOR low and active Chip Enables and AD0 and AD1 low, or IO/M high, RD low, active chip enables, and AD0 and AD1, LOW. Port B: This general purpose I/O port is identical to Port A except that it is selected by a 1 latched from AD0 and a 0 from AD1. Reset: An input high causes all pins in Port A and B to assume input-mode. (Clear DDR Register.) I/O Read: When the Chip Enables are active, a low on IOR will output the selected I/O port onto the AD bus. IOR low performs the same function as the combination IO/M high and RD low. When IOR is not used in a system, IOR should be tied to VCC. Voltage: +5 Volt Ground: Ground Reference. AD0-7 12-19 I A8-10 CE1,CE2 21, 22, 23 1, 2 l I IO/M 7 I RD 9 I IOW 10 I CLK 3 I READY 6 O PA0-7 24-31 I/O PB0-7 32-39 I/O RESET 4 l IOR 8 I VDD GND 40 20 I I * ALE must be clocked once after power up. 11-2 Specifications HS-83C55RH Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VDD+0.3V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC Typical Derating Factor . . . . . . . . . .1.5mA/MHz Increase in IDDOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Reliability Information Thermal Resistance ja jc Braze Seal DIP Package . . . . . . . . . . . . . 25.8oC/W 9.9oC/W Maximum Package Power Dissipation at +125oC Braze Seal DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.94W CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VDD -0.5V to VDD TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS All Devices are Guaranteed at Worst Case Limits and Over Radiation. Dynamic Current is Proportional to Operating Frequency. GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 7, 8A, 8B LIMITS TEMPERATURE -55oC, +125oC +25oC, or MIN -1.0 4.25 -10 MAX 1.0 0.5 10 100 5.0 UNITS A A V V A A A mA/MHz - PARAMETERS Input Leakage Current SYMBOL IIH IIL CONDITIONS VDD = 5.25V, VIN = 0V Pin Under Test = VDD VDD = 5.25V, VIN = 5.25V Pin Under Test = 0V VDD = 4.75V, IOH = -2.0mA VDD = 5.25V, IOL = 2.0mA, VDD = 5.25V, VIN = 0V VDD = 5.25V, VIN = 5.25V VDD = 5.25V VDD = 5.25V, f = 1MHz VDD = 4.75V and 5.25V, VIH = VDD - 0.5, VIL = 0.8V -55oC, +25oC, or +125oC -55oC, +25oC, or +125oC -55oC, +25oC, or +125oC -55oC, +25oC, or +125oC -55oC, +25oC, or +125oC -55oC, +25oC, or +125oC -55oC, +25oC, or +125oC -55oC, +25oC, or +125oC High Level Output Voltage Low Level Output Voltage Output Leakage Current VOH VOL IOZL IOZH Static Current Dynamic Current Functional Tests IDDSB IDDOP FT TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS AC Tests are Guaranteed Through Functional Testing with the Clock Period Equal to 500ns. TRDE + TRDF are the Only Read and Record Parameters. Output Timings are Measured with a Capacitive Load CL = 170pF, VIH = 4.25, and VIL = 0.8V GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 LIMITS TEMPERATURE -55 C, +25 C, +125 C -55o C, +25 C, +125 C +25oC, o o o o o o PARAMETERS Data Bus Float After Read Read Control to Data Bus Enable Clock Pulse Width Low Clock Pulse Width High Clock Rise and Fall Times Address to Latch Setup Time Address Hold Time After Latch Latch to Read/Write Control SYMBOL TRDF TRDE T1 T2 TR, TF TAL TLA TLC MIN 0 10 40 70 60 60 140 MAX 110 100 - UNITS ns ns ns ns ns ns ns ns -55oC, o +125oC o -55 C, +25 C, +125 C -55oC, -55oC, o +25oC, +25oC, o +125oC +125oC o -55 C, +25 C, +125 C -55oC, +25oC, +125oC 11-3 Specifications HS-83C55RH TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) AC Tests are Guaranteed Through Functional Testing with the Clock Period Equal to 500ns. TRDE + TRDF are the Only Read and Record Parameters. Output Timings are Measured with a Capacitive Load CL = 170pF, VIH = 4.25, and VIL = 0.8V GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 LIMITS TEMPERATURE -55 C, +25 C, +125 C -55oC, -55o o o o o PARAMETERS Valid Out Delay from Read Control (Note 1) Address Stable to Data Out Valid (Note 2) Latch Enable Width Read/Write Control of Latch Enable Read/Write Control Width Data In to Write Setup Time Data In Hold Time After Write Write to Port Output Port Input Setup Time Port Input Hold Time Ready Hold Time Address CE to Ready Recovery Time Between Controls NOTES: 1. Or TAD - (TAL + TLC), whichever is greater. SYMBOL TRD TAD TLL TCL TCC TDW TWD TWP TPR TRP TRYH TARY TRV MIN 120 40 200 150 10 50 50 0 300 MAX 140 340 300 160 160 - UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns +25oC, o o +125oC o o C, +25 C, +125 C -55 C, +25 C, +125 C -55oC, -55o o +25oC, o o +125oC o o C, +25 C, +125 C -55 C, +25 C, +125 C -55oC, -55o o +25oC, o o +125oC o o C, +25 C, +125 C -55 C, +25 C, +125 C -55oC, -55oC, o +25oC, +25oC, o +125oC +125oC o -55 C, +25 C, +125 C 2. Defines ALE to Data Out Valid in conjunction with TAL. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTE 1) CONDITIONS VDD = Open, f = 1MHz VDD = Open, f = 1MHz VDD = Open, f = 1MHz LIMITS TEMPERATURE TA = +25oC o PARAMETERS Input Capacitance I/O Capacitance Output Capacitance NOTE: SYMBOL CIN CI/O COUT MIN - MAX 10 12 10 UNITS pF pF pF TA = +25 C TA = +25oC 1. All measurements referenced to device ground. TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS NOTE: The post irradiation test conditions and limits are the same as those listed in Table 1 and 2. TABLE 5. BURN-IN DELTA PARAMETERS (+25oC) PARAMETER Output Low Voltage Output High Voltage Input Leakage Current Input Leakage Current Static Current SYMBOL VOL VOH IIL IIH IDDSB DELTA LIMITS 60mV 400mV 100nA 100nA 30A 11-4 HS-83C55RH A.C. Testing Input, Output Waveform INPUT/OUTPUT INPUT VIH VDD 2 VIL VDD 2 VOL OUTPUT VOH DEVICE UNDER TEST TEST POINT CL* = 100pF A.C. Testing Load Circuit (Note 1) A.C. TESTING: All input signals must switch between VIL max and VIH min, tr and tf must be less than or equal to 15ns. * CL includes stray and jig capacitance. NOTES: 1. Output timings are measured with purely capacitive load. 2. Devices screened to more rigorous electrical specifiecations are available. Contact your nearest Intersil representative for details. Waveforms ROM READ AND I/O READ AND WRITE tCYC T1 T2 CLK A8-10 IO/M ADDRESS tAD AD0-7 ADDRESS DATA (CE1 = 0 CE2 = 1) tLL ALE tAL RD IOR tLC tDW tCC IOW tCL tWD tRDE tRD tRV tRDF tLA 83C55RH CLOCK SPECIFICATIONS tr T2 tf T1 tCYC 11-5 HS-83C55RH Waveforms (Continued) INPUT MODE RD OR IOR tPR tRP PORT INPUT DATA* BUS * DATA BUS TIMING IS SHOWN IN FIGURE 4. OUTPUT MODE IOW tWP PORT OUTPUT GLITCH FREE OUTPUT DATA * BUS * DATA BUS TIMING IS SHOWN IN FIGURE 4. WAIT STATE CLK tAL (CE2 = 1 CE1 = 0) ALE READY tARY tRYH NOTE: READY = 0 11-6 HS-83C55RH Burn-In Circuits HS-83C55RH 40 PIN DIP VDD HS-83C55RH 40 PIN DIP R1 1 2 3 4 5 N/C 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 C3 C2 C1 F0 F1 F2 F3 F4 F5 F6 F7 F11 1 2 3 4 N/C 5 N/C 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 F0 F1 F2 F3 F4 F5 F6 F7 F0 F1 F2 F3 F4 F5 F6 F7 F10 F9 F8 VDD STATIC NOTES: VDD = 10V 10% 16K ROM TA Min = 125oC All Resistors are 10k 10%, 1.4 Watt Part is static sensitive. Voltage must be ramped. C1 C2 C3 DYNAMIC NOTES: VDD = 10V 10% 16K ROM TA = 125oC C2 = C3 R1 = 100K 10%, 1/4 Watt. All other resistors 10K 10%, 1/4 Watt. Part is static sensitive. Voltage must be ramped. C2 thru C3 = 200kHz and have 50% duty cycles. C1 = 200kHz and have 20% duty cycle. F0 = 100kHz, F1 = F0/2, F2 = F1/2 . . . F11 = F10/2 Frequencies Fn defined by: Fn = F(n-1)/2 where F0 = 100kHz e.g. F1 = 50kHz, F2 = 25kHz . . . All Fn's have 50% duty cycle. Part is static sensitive. 11-7 HS-83C55RH Irradiation Circuit VDD = 5V 1 2 3 4 5 N/C 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS = GND 11-8 HS-83C55RH Radiation Screening Procedure 1. A random sample of two dice per wafer is drawn from the wafer lot. Wafer identity is retained. 2. The sample die shall be assembled and tested for functionality in a ceramic DIP. 3. The sample devices shall be subjected to a Total Dose Radiation level of 1 x 105 Rad(Si) +10% from a Gammacell 220 cobalt 60 source or equivalent. The devices will be powered with VSUPPLY = +5V. The dose rate shall be between 50 rads/sec and 300 rads/sec. 4. The Irradiation Circuit is shown on a previous page. 5. The sample devices shall be started into test within 1 hour of irradiation and have completed test within 2 hours of irradiation. The wafers are accepted only if the sample, exclusive of non-radiation failures, meets all electrical specifications at room temperature. 6. Radiation screening to a higher total dose is available. Customers should contact their closest Intersil Representative for de- Radiation Effects The HS-83C55RH has been designed to survive in a radiation environment and to meet the electrical characteristics. Latch-up free operation is achieved by the use of epitaxial starting material. Improved total dose hardness is obtained with special low temperature processing cycles. On a production basis, Intersil performs screens for total dose hardness to a level of 1 x 105 Rad-Si. Transient radiation tests have shown the following results: 1. Latch-up free to doses 1 x 1012 rads/sec. 2. Upset (loss of stored data 1 x 108 rads/sec. Intersil - Space Level Product Flow -Q (Note 1) SEM - Traceable to Diffusion Method 2018 Wafer Lot Acceptance Method 5007 Internal Visual Inspection Method 2010, Condition A Gamma Radiation Assurance Tests Method 1019 Nondestructive Bond Pull Method 2023 Customer Pre-Cap Visual Inspection (Note 2) Temperature Cycling Method 1010, Condition C Constant Acceleration Method 2001, Condition E Min, Y1 Particle Impact Noise Detection Method 2020, Condition A Electrical Tests Intersil's Option Serialization X-Ray Inspection Method 2012 Electrical Tests Subgroup 1; Read and Record (TO) Static Burn-In Method 1015, Condition B, 72 Hours, +125oC Minimum Electrical Tests Subgroup 1; Read and Record (T1) Burn-In Delta Calculation (T0-T1) PDA Calculation 3% Subgroup 7 5% Subgroups 1, 7, Dynamic Burn-In Method 1015 Condition D, 240 Hours, +125oC (Note 3) Electrical Tests Subgroup 1; Read and Record (T2) NOTES: Alternate Group A Subgroups 1, 7, 9; Method 5005; Para 3.5.1.1 Burn-In Delta Calculation (TO-T2) PDA Calculation 3% Subgroup 7 5% Subgroups 1, 7, Electrical Test Subgroup 3; Read and Record Alternate Group A Subgroups 3, 8B, 11; Method 5005; Para 3.5.1.1 Marking Electrical Tests Subgroup 2; Read and Record Alternate Group A Subgroups 2, 8A, 10; Method 5005; Para 3.5.1.1 Gross Leak Method 1014, 100% Fine Leak Method 1014, 100% Customer Source Inspection (Note 2) Group B Inspection Method 5005 (Note 2) End-Point Electrical Parameters: B-5/ Subgroups 1, 2, 3, 7, 8A, 8B, 9, 10, 11 B-6; Subgroups 1, 7, 9 Group D Inspection Method 5005 (Notes 2, 4) End-Point Electrical Parameters: Subgroups 1, 7, 9 External Visual Inspection Method 2009 Data Package Generation (Note 5) 1. The notes of Method 5004, Table 1 Shall apply; unless otherwise specified. 2. These steps are optional and should be listed on the individual purchase order(s), when required. 3. Intersil reserves the right of performing burn-in time temperature regression as defined by Table 1 of Method 1015 4. For group D, subgroup 3 inspection of package configurations which utilize a gold plated lid in its construction; the inspection criteria for illegible markings criteria of Method 1010, paragraph 3.3 and of Method 1004, paragraph 3.8.a shall not apply. 5. Data package contains: Wafer lot acceptance report (including SEM report) Assembly attributes (Post Seal) X-ray report and film Test attributes (includes Group A) Test variables data Shippable serial number list Radiation testing certificate of conformance 11-9 HS-83C55RH Metallization Topology DIE DIMENSIONS: 179.1 x 189.0 x 14 1mils METALLIZATION: Type: Si Al Thickness: 11kA 2kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA DIE ATTACH: Material: Gold Silicon Eutectic Alloy Temperature: Ceramic DIP - 460oC (Max) Metallization Mask Layout HS-83C55RH (4) RESET (40) VDD (39) PB7 (38) PB6 (37) PB5 (2) CE2 (36) PB4 (3) CLK (1) CE1 (35) PB3 READY (6) (34) PB2 IO/M (7) IOR (8) RD (9) IOW (10) ALE (11) (33) PB1 (32) PB0 (31) PA7 (30) PA6 (29) PA5 AD0 (12) (28) PA4 (27) PA3 AD1 (13) AD2 (14) (26) PA2 AD3 (15) GND (20) AD4 (16) AD5 (17) AD6 (18) AD7 (19) A10 (23) PA0 (24) PA1 (25) A8 (21) A9 (22) 11-10 HS-83C55RH Functional Description ROM Section The HS-83C55RH contains an 8-bit address latch which allows it to interface directly to the HS-80C85RH Microprocessor without additional hardware. The R0M section of the Chip is addressed by an 11-bit address and the Chip Enables. The address and levels on the Chip Enable pins are latched into the address latches on the falling edge of ALE. If the latched Chip Enables are active and IO/M is low when RD goes low, the contents of the R0M location addressed by the latched address are put out through AD0-7 output buffers. I/O Section The I/O section of the chip is addressed by the latched value of AD0-1. Two 8-bit Data Direction Registers (DDR) in the HS-83C55RH determine the input/output status of each pin in the corresponding ports. A "O" in a particular bit position of a DDR signifies that the corresponding I/O port bit is in the input mode. A "1" in a particular bit position signifies that the corresponding I/O port bit is in the output mode. In this manner the I/O ports of the HS-83C55RH are bit-by-bit programmable as inputs or outputs. The table summarizes port and DDR designation. DDR's Cannot be read. AD1 0 0 1 1 AD0 0 1 0 1 Port A Port B Port A Data Direction Register (DDR A) Port B Data Direction Register (DDR B) READ PA Write PA = (IOW = 0) (Chip Enables Active) (Port A Address Selected) Write DDR A = (IOW = 0) (Chip Enables Active) (DDR A Address Selected) Read PA = {[(IO/M = 1) (RD = 0)] + (IOR = 0)} (Chip Enables Active) (Port A Address Selected) NOTE: Write PA is not qualified by IO/M. System Interface with HS-8OC85RH A system using the HS-83C55RH can use either one of the two I/O Interface techniques: * Standard I/O * Memory Mapped I/O If a standard I/O technique is used, the system can use the feature of both CE2 and CE1. By using a combination of unused address lines A11-15 and the Chip Enable inputs, the system can use up to 5 each HS-83C55RHs without requiring a CE decoder. See Figure 3. If a memory mapped I/O approach is used the HS-83C55RH will be selected by the combination of both the Chip Enables and IO/M using AD8-15 address lines. See Figure 2. HS-83C55RH ONE BIT OF PORT A AND DDR A: D0 OUTPUT LATCH CLK INTERNAL DATA BUS D Q OUTPUT ENABLE WRITE PA DDR LATCH PA0 PIN Q Selection D0 D CLR CLK RESET D0 WRITE DDR A When IOW goes low and the Chip Enables are active, the data on the AD0-7 is written into the I/O port selected by the latched value of AD0-1. During this operation all I/O bits of selected port are affected, regardless of their I/O mode and the state of IO/M. The actual output level does not change until IOW returns high (glitch free output). A port can be read out when the latched Chip Enables are active and either RD goes low with IO/M high, or IOR goes low. Both input and output mode bits of a selected port will appear on lines AD0-7. To clarify the function of the I/O ports and Data Direction Registers, Figure 1 shows the configuration of one bit of PORT A and DDR A. The same logic applies to PORT B and DDR B. Note that hardware RESET or writing a zero to the DDR latch will cause the output latch's output buffer to be disabled, preventing the data in the output latch from being passed through to the pin. This is equivalent to putting the port in the input mode. Note also that the data can be written to the Output Latch even though the Output Buffer has been disabled. This enables a port to be initialized with a value prior to enabling the output. Figure 1 also shows that the contents of PORT A and PORT B can be read even when the ports are configured as outputs. FIGURE 1. HS-83C55RH ONE BIT OF PORT A AND DDR A A8-15 AD0-7 ALE RD HS-83C55RH WR CLK (2) READY IO/M VDD ALE RD IOW CLK READY IO/M CE AD0-7 A8-10 IOR VDD HS-83C55RH FIGURE 2. HS-83C55RH IN HS-80C85RH SYSTEM (MEMORY\MAPPED I/O) 11-11 HS-83C55RH A8-10 AD0-7 VDD IOR A8-10 AD0-7 VDD IOR A8-10 AD0-7 VDD IOR A8-10 AD0-7 VDD IOR A8-10 AD0-7 AD0-7 CLK (2) A8-15 VDD READY IOR IO/M ALE HS-83C55RH NOTE: Use CE1, for the first HS-83C55RH in the system, and CE2 for the other HS-83C55RH's. Permits up Is 5 HS-83C55RH's in a system without CE decoder. FIGURE 3. HS-83C55RH IN HS-8OC85RH SYSTEM (STANDARD I/O) WR RD 11-12 HS-83C55RH (2K BYTES) CE1 IO/M READY CLK IOW RD ALE A11 HS-83C55RH (2K BYTES) CE2 IO/M READY CLK IOW RD ALE A12 HS-83C55RH (2K BYTES) CE2 IO/M READY CLK IOW RD ALE A13 HS-83C55RH (2K BYTES) CE2 IO/M READY CLK IOW RD ALE A14 HS-83C55RH (2K BYTES) CE2 IO/M READY CLK IOW RD ALE A15 |
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